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IS61LV2568L
256K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
* * * * * * * * * High-speed access time: 8, 10 ns Operating Current: 50mA (typ.) Standby Current: 700A (typ.) Multiple center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options CE power-down TTL compatible inputs and outputs Single 3.3V power supply Packages available: - 36-pin 400-mil SOJ - 44-pin TSOP (Type II) Lead-free available
ISSI
JULY 2005
(R)
DESCRIPTION The ISSI IS61LV2568L is a very high-speed, low power,
262,144-word by 8-bit CMOS static RAM. The IS61LV2568L is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 36mW (max.) with CMOS input levels. The IS61LV2568L operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV2568L is available in 36-pin 400-mil SOJ and 44-pin TSOP (Type II) packages.
*
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K X 8 MEMORY ARRAY
VDD GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
1
IS61LV2568L
PIN CONFIGURATION
36-Pin SOJ 44-Pin TSOP (Type II)
ISSI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A5 A6 A7 A8 OE I/O7 I/O6 GND VDD I/O5 I/O4 A9 A10 A11 A12 NC NC
NC NC A4 A3 A2 A1 A0 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A17 A16 A15 A14 A13 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A5 A6 A7 A8 OE I/O7 I/O6 GND VDD I/O5 I/O4 A9 A10 A11 A12 NC NC NC NC
(R)
A4 A3 A2 A1 A0 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A17 A16 A15 A14 A13
PIN DESCRIPTIONS
A0-A17 CE OE WE I/O0-I/O7 VDD GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground No Connection
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
IS61LV2568L
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write WE X H H L CE H L L L OE X H L X I/O Operation High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ICC ICC ICC
ISSI
(R)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VTERM TSTG PD Parameter Supply voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.5 to +4.0 -0.5 to VDD + 0.5 -65 to +150 1.0 Unit V V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD (8ns) 3.3V +10%,-5% VDD (10 ns) 3.3V + 10% 3.3V + 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage Input Leakage Output Leakage
(1)
Test Conditions VDD = Min., IOH = -4.0 mA VDD = Min., IOL = 8.0 mA
Min. 2.4 -- 2.0 -0.3
Max. -- 0.4 VDD + 0.3 0.8 1 1
Unit V V V V A A
GND VIN VDD GND VOUT VDD, Outputs Disabled
-1 -1
Note: 1. VIL(min) = -0.3V (DC); VIL(min) = -2.0V (pulse width - 2.0 ns). VIH(max) = VDD + 0.3V (DC); VIH(max) = VDD + 2.0V (pulse width - 2.0 ns).
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
3
IS61LV2568L
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC Parameter VDD Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = Max. VDD = Max., VIN = VIH or VIL CE VIH, f = max VDD = Max., CE VDD - 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 Com. Ind. typ.(2) Com. Ind. Com. Ind. typ.(2) -8 ns Min. Max. -- -- -- 65 50 30 -10 ns Min. Max. -- -- -- -- -- -- -- -- 60 65 50 25 30 3 4 700
ISSI
Unit mA
(R)
ISB1
mA
ISB2
-- --
3 700
mA mA A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD=3.3V, TA=250C. Not 100% tested.
CAPACITANCE(1,2)
Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
IS61LV2568L
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
ISSI
(R)
AC TEST LOADS
319
ZO = 50 OUTPUT 30 pF Including jig and scope 50 1.5V
3.3V
OUTPUT 5 pF Including jig and scope
Figure 2
353
Figure 1
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
5
IS61LV2568L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter - 8 ns Min. Max 8 -- 2.5 -- -- 0 0 3.5 0 -- 8 -- 8 3.5 -- 3.5 -- 3.5 -10 ns Min. Max. 10 -- 2.5 -- -- 0 0 3 0 -- 10 -- 10 4 -- 4 -- 4
ISSI
Unit ns ns ns ns ns ns ns ns ns
(R)
tRC tAA tOHA tACE tDOE tHZOE tLZCE
(2)
Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output CE to Low-Z Output
tLZOE(2) OE to Low-Z Output
(2)
tHZCE(2) CE to High-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
IS61LV2568L
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t RC
ADDRESS
ISSI
(R)
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
OE
t OHA
t DOE
CE
t HZOE
t LZOE t ACE t LZCE t HZCE
DATA VALID
CE_RD2.eps
DOUT
HIGH-Z
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
7
IS61LV2568L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE Pulse Width (OE = HIGH) WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End
(3)
ISSI
- 8 ns Min. Max 8 7 7 0 0 6 6.5 4 0 -- 0 -- -- -- -- -- -- -- -- -- 3 -- -10 ns Min. Max. 10 8 8 0 0 7 8 5 0 -- 0 -- -- -- -- -- -- -- -- -- 4 -- Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE
(3)
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
IS61LV2568L
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t HZWE t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Note: 1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
9
IS61LV2568L
AC WAVEFORMS WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
t HA
OE
CE
LOW
t AW t PWE1
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
LOW
t AW t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write.
10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
IS61LV2568L
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 8 10 Order Part No. IS61LV2568L-8K IS61LV2568L-8T IS61LV2568L-10T IS61LV2568L-10TL Package 400-mil SOJ TSOP (Type II) TSOP (Type II) TSOP (Type II), Lead-free
ISSI
(R)
Industrial Range: -40C to +85C
Speed (ns) 10 Order Part No. IS61LV2568L-10KI IS61LV2568L-10KLI Package 400-mil SOJ 400-mil SOJ, Lead-free
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. C 07/25/05
11
PACKAGING INFORMATION
400-mil Plastic SOJ Package Code: K
ISSI
Notes: 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027.
(R)
N
N/2+1
E1
E
1
N/2
D A
SEATING PLANE
b
C A2
e
B
A1
E2
Symbol No. Leads A A1 A2 B b C D E E1 E2 e
Millimeters Inches Min Max Min Max (N) 28 3.25 3.75 0.128 0.148 0.64 -- 0.025 -- 2.08 -- 0.082 -- 0.38 0.51 0.015 0.020 0.66 0.81 0.026 0.032 0.18 0.33 0.007 0.013 18.29 18.54 0.720 0.730 11.05 11.30 0.435 0.445 10.03 10.29 0.395 0.405 9.40 BSC 0.370 BSC 1.27 BSC 0.050 BSC
Millimeters Min Max 32 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 20.82 21.08 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC
Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.820 0.830 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC
Millimeters Min Max 36 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 23.37 23.62 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC
Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 0.920 0.930 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 10/29/03
PACKAGING INFORMATION
ISSI
Millimeters Min Max 42 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 27.18 27.43 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC Inches Min Max 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.070 1.080 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Millimeters Min Max 44 3.25 3.75 0.64 -- 2.08 -- 0.38 0.51 0.66 0.81 0.18 0.33 28.45 28.70 11.05 11.30 10.03 10.29 9.40 BSC 1.27 BSC 0.128 0.148 0.025 -- 0.082 -- 0.015 0.020 0.026 0.032 0.007 0.013 1.120 1.130 0.435 0.445 0.395 0.405 0.370 BSC 0.050 BSC Inches Min Max
(R)
Millimeters Inches Symbol Min Max Min Max No. Leads (N) 40 A 3.25 3.75 0.128 0.148 A1 0.64 -- 0.025 -- A2 2.08 -- 0.082 -- B 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 E 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 10/29/03
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
ISSI
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
N/2+1
E1
E
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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